True or False: Automated Validation Rules

Abstract

This presentation is a reprise of one given at this year’s MBSE Cyber Experience Symposium. The use of automated validation of system models enables modelers to focus on value-added tasks by reducing the administrative drag of assessing conformance to modeling style and checking for omissions and inconsistencies. Each rule is an atomic test that returns a Boolean for any tested element: TRUE for those that satisfy the rule, FALSE for those that violate it. 

This presentation will discuss best practices and specific techniques and patterns that have emerged from the stewardship of the SAIC Digital Engineering Validation Tool, the largest, freely-available SysML validation ruleset currently available. It will also provide insights into how to craft a holistic set of rules that collectively enforce a given modeling methodology and style.   

Speaker Info

Michael J. Vinarcik, P.E., ESEP-Acq is the Digital Architecture and Requirements Engineering (DARE) Director in SAIC's Engineering Innovation Factory, an adjunct professor at the University of Detroit Mercy and CIDESI (Mexico). He has over thirty years of automotive and defense engineering experience and presents regularly at national and regional conferences. Michael has contributed to several books, most notably Taguchi’s Quality Engineering Handbook and the MBSE chapter for the third edition of Systems Engineering: Principles and Practice. He is a Fellow of the Engineering Society of Detroit, the President and Founder of Sigma Theta Mu, the systems honor society.